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Use of three-dimensional flash memory is growing rapidly in both consumer and enterprise segments. In such flash memory, two different data states exist on each memory cell. An erased data state refers to either a charge “0” state or a charge “1” state. A programmed data state refers to a charge between “0” and “1.” Flash memory cell arrays employ bit lines and word lines for accessing data from the memory cells. Word lines extend across the array to connect memory cells on different rows while bit lines extend within columns of the array to read data from memory cells.
During a read operation, a selected word line is activated to turn on the memory cells connected to the word line and turned off the others. The selected memory cells will share a series of bit lines that connect the cells. Data from each cell will be sensed on the bit lines. A sense amplifier circuit detects the voltage difference between the selected memory cells. The sense amplifier is able to measure a voltage difference between 0.5V and 1.5V, which is small compared to the supply voltage of a system (e.g., 3V).
As a system (e.g., a processor) requires more read operations, the time necessary for a read operation increases. This is a problem because a typical system-wide cache has a limited size. For example, in a first system, a cache and a system are coupled to a memory device. In a second system, the cache is removed and the memory device is coupled directly to the system. In the second system, the memory device now stores all non-cache memory access data which used to be stored in the cache. The cache in the second system is then unable to store data. This results in slower read operations in the second system. In the worst case, the read operations can take a considerable amount of time due to some bits not being stored in the cache.Q:
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